1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory system with a plurality of erase blocks.
2. Description of the Related Art
A memory cell array of a Flash Electrically Erasable Programmable Read Only Memory, or Flash EEPROM, which utilizes a one transistor memory cell, is about the same size as the Ultra Violet ray Erasable Programmable Read Only Memory, or UVEPROM. This makes the chip fabrication cost for the Flash EEPROM far smaller than that of the conventional EEPROM which utilizes a two transistor memory cell. In the Flash EEPROM, floating gate memory cell transistors are connected to a bit line without a transfer gate transistor. This is the structural barrier to achieving small sector erase operation which is long awaited by users who want to replace magnetic storage devices with the Flash EEPROM.
The Flash EEPROM has a problem called "drain disturb". This is a gradual disappearing of programmed data stored in one memory cell transistor, caused by a program operation of the other memory cell transistors which are commonly connected with the former one.
The programming operation of the Flash EEPROM is conducted by setting the drain electrode of the selected memory cell transistor to 5[V] and the control gate to 10[V], which causes hot carrier injection from the drain to the floating gate making the threshold voltage higher. To the unselected memory cell transistor which is connected to the selected bit line, the drain electrode is set to 5[V], and control gate is set to 0[V], which causes unwanted tunneling current from the floating gate to the drain. Due to this tunneling current, the threshold voltage of the unselected memory cell transistor is lowered, such that "drain disturb" occurs.
Such drain stress time is increasingly multiplied with the increase in the number of erase blocks. The worst case occurs when one memory cell transistor is programmed only once, and all other memory cell transistors connected with the former memory cell transistor by a bit line are erased and programmed 100,000 times (which is an assured limitation set by a manufacturer of the Flash EEPROM). In this case, the, drain stress time is 100,000 times longer than conventional EEPROM with only one erase block.